|
This paper proposes generative machine learning models to synthesize VLSI layouts through a pattern generation framework that reduces the challenging creation problem into two simpler subproblems with the aid of an efficient squish pattern representation. The problem is treated by designing an innovative transforming convolutional auto-encoder in TCAE architecture, aiming to generate efficient and representative pattern shapes. The paper introduces a GAN-guided TCAE ML analysis that targets massive DRC-clean and content-specific pattern generation following certain design rules, without losing pattern library diversity. Through experiments on 7nm EUV designs, the authors demonstrate that each latent vector node in TCAE has a real physical meaning in layout domain and transformations on latent vectors can produce additional topologies of interest. Results show that the generated pattern library exhibits larger pattern number and pattern diversity compared to the traditional state-of-the-art industry layout generator.
The IEEE Transactions on Semiconductor Manufacturing is a quarterly peer-reviewed scientific journal published by the IEEE. It covers research on semiconductor device fabrication, including simulation and modeling from the factory to the detailed process level, defect control, yield analysis and optimization, production planning and scheduling, environmental issues in semiconductor manufacturing, and manufacturability improvement.
|
